As technology has evolved, semiconductor devices have become smaller and more dense, which has resulted in corresponding increases in overall chip failure rates, which in turn results in uncompetitive situations for chip manufacturers. There is therefore a need and desire by manufacturers of chips and semiconductor devices to be able to readily identify and eliminate the use of defective chips before the defective chips are finally mounted in a product.
Burn-in processes have evolved and have been developed in an effort to identify and eliminate the use of defective chips. During the burn-in process, normally a chip carrier is provided for testing the chips. The chip carrier has electrical contacts which correspond to the electrical contacts on the semiconductor chip. It is desirable for the carrier contacts to be mechanically weak but strong enough for holding the semiconductor chip in place during testing and to maintain good electrical connections. The chip is normally positioned on the chip carrier so that the electrical contacts, e.g., solder balls, on the chip are aligned with the corresponding contacts on the carrier and then the solder balls are partially reflowed to make electrical connections between the chip and the carrier.
It is therefore desirable to provide for the easy removal of the chip from the chip carrier after the burnin test so that defective chips can be discarded or used elsewhere and good chips can be identified and used permanently. The chip carrier can also then be re-used for testing of further similar chips. It is thus desirable to be able to temporarily attach the semiconductor chip to the carrier in such a way that it can be readily separated after the burn-in test without mechanical damage to either the chip or the chip carrier.
In general, the burn-in test exercises or operates the chip at elevated voltage and temperature levels for an extended period of time in order to simulate the actual operation of the chip for its normal and expected lifetime in a final product. The electrical responses of the chip are also monitored and thus there is assurance that the chip will perform its operations during its expected life without failing. This procedure is well known to those familiar with the semiconductor technology.
A variety of processes and techniques have been devised and described in the art to form a temporary connection between semiconductor chips and carriers, so as to be able to readily separate the chip and the carrier after burn-in tests have been conducted. For Example:
U.S. Pat. No. 5,237,269 (Aimi et al.) issued Aug. 17, 1993, and assigned to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, describes connections between circuit chips and temporary carriers for use in burn-in tests whereby the pads on a ceramic substrate are covered by an overlay of non-wettable material to which solder will not adhere whereby the overlay has an opening through which solder flows to make a restricted joint between the solder ball of the chip and the lead line of the carrier;
U.S. patent application Ser. No. 24,549, entitled "Method And Apparatus For In-Situ Testing of Integrated Circuit Chips", filed Mar. 1, 1993, (Attorney Docket No. EN9-93-001), assigned to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, provides a method and apparatus for in-situ testing of integrated circuit chips whereby the electrical contacts between the semiconductor chips to be tested and those of the carrier are made by means of dendritic surfaces such that there are vertical projections between the contacts resulting in a fracturable joint;
U.S. Pat. No. 5,173,451 (Kinsman, et al.) issued Dec. 22, 1992, to Micron Technology Inc., provides for a soft bond for semiconductor dies wherein a reduced sized wire bond is used to create a readily fracturable joint to separate the chip from the carrier such that less bonding force is required to retain the lead wires to the carrier than the attachment strength of the pads on the chip;
U.S. Pat. No. 5,007,163 (Pope et al.), issued Apr. 16, 1991, to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, describes a non-destructive method of performing electrical burn-in testing of semiconductor chips by making use of a eutectic mixture which remains liquid at certain temperatures for forming a readily fracturable connection;
IBM Technical Disclosure Bulletin, "Burn-In/In Situ Testing of Computer Chips", Volume 36, No. 3, pp. 229-231 (March 1993), describes burn-in testing of semiconductor chips in which no permanent connection between the chip contact and the substrate is required which results from limited area pads with smaller solder ball carrier surfaces; and
IBM Technical Disclosure Bulletin, "Wafer Level Test And Burn-In", Volume 34, No. 8, pp. 401-404 (January 1992), describes burn-in testing of a wafer containing semiconductor chips on a carrier such that the contact pads between the contacts are made of two-level solder structure with a small contact area between the two levels. The two levels are comprised of high melting point solder and low melting point solder.
The methods and devices described in these aforementioned references are useful in many applications where it is desired to have detachable connections between the contacts of a carrier and chip for chip burnin situations, but this may not be useful in all circumstances. For example, for use in testing chips for multilayer ceramic devices which have a large number of connections, in some cases up to 2,800 connections, known methods are limited and may not be usable. With this large number of connections the overall strength of the connection between the carrier and chip is relatively high which may result in damage to the chip or the carrier upon the removal of the chip from the carrier. Thus there is a need for every individual connection to be relatively weak. It may be difficult, if not impossible, for example, to design a mask with any precision that will have the needed definition for such a large number of small holes to accommodate this number of connections. It is also difficult with the required number of smaller holes to have the solder balls on the chips to be accurately positioned in the holes. The presently proposed processes and chip carrier do not require changes to the presently configured chip solder balls.
Other references have been identified which disclose a variety of techniques for providing temporary or detachable connections between two surfaces in general, or as may be applied in particular applications to semiconductor devices. These include for example:
U.S. Pat. No. 5,170,930 (Dolbear et al.), issued Dec. 15, 1992, to Microelectronics and Computer Technology Corporation, describes the use of a thermally and electrically conductive paste for making a detachable connection between two surfaces;
U.S. Pat. No. 4,740,099 (Philipoussi), issued Apr. 26, 1988, to Societe Nationale Industrielle Aerospatiale, describes an arrangement for temporarily soldering plates together such that they can be mechanically released. This is accomplished by restricting the areas to which the solder can be applied. The fracturable connection results from areas which are limited for the application of solder;
U.S. Pat. No. 4,526,859 (Christensen, et al.), issued Dec. 12, 1983, to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, discloses a method of selectively metallizing a ceramic substrate provided with a metallization pattern using photoresist processing; and
U.S. Pat. No. 4,360,142 (Carpenter et al.), issued Nov. 23, 1982, to International Business Machines Corporation, the disclosure of which is incorporated herein by reference, describes solder connections for electrically joining semiconductor devices to a supporting substrate.
IBM Technical Disclosure Bulletin, Vol. 35, No. 4A, pages 25-27 (September 1992), discloses an interposer removal tool, where an apparatus and method were developed to remove the interposers from a substrate.
Although it would appear that the teachings of these prior art references have found some usefulness in some situations and applications where a detachable connection is required, they do not provide completely satisfactory solutions for all situations, particularly where the increasing complexities and miniature size of semiconductor devices is concerned.
All similar previous removal methods of removing chips are known to cause chip damage and/or reliability concerns. This invention however covers apparatus and process developed to remove die or chip from a surrogate substrate or chip carrier without any damage to either.
It is therefore desirable to provide a new process and apparatus to separate a chip from its temporary chip carrier after the burn-in process or testing of the chip has taken place, which has not been described in the aforementioned art. This invention results in beneficial and practical testing of chips and readily permits the identification of those chips which may be defective and those which are good and can be used in final products.
It is also desirable to provide a new semiconductor chip carrier which can be re-used in the testing and identification of defective and good chips. This invention allows the safe removal of semiconductor devices which are sometimes called known-good-die (KGD) after they have been burnt-in and/or tested.